This research effort involves the design and fabrication of a new reconfigurable parallel machine for machine vision. The ``Proteus'' system architecture is a highly parallel MIMD, multiple instruction multiple data, machine with 256 to 1,024 processors that can be operated in single program multiple data (SPMD) or multiple program multiple data (MPMD) modes. The hardware is highly optimized for large grain messaging.
The proposed architecture is a reconfigurable network of nodes. A reconfigurable interconnection network (RCN) provides flexible communication among the processor nodes and the input/output devices. The reconfiguration algorithm permits embedding of arbitrary permutation in the structure. Thus the data-flow patterns of an application can be directly mapped in hardware.
The hardware is organized in a hierarchical fashion. It employs redundancy to facilitate some degree of fault tolerance and testing. The system is capable of detecting, locating and reconfiguring a permanently faulty subsystem on-line with very small latency.
The software supports an interactive user-friendly environment including a task translator, loader, debugger and simulator. Algorithms are expressed as program graphs. The graph structure is then mapped onto the physical hardware by a greedy allocation algorithm that tries to distribute the load as evenly as possible while minimizing communication cost.
A 46 processor prototype configuration has been built and currently being used for a variety of applications including morphological image processing, signal processing applications such as FFT, and parallel volume rendering.
Principal Investigators: Shapiro, Somani, Haralick