Lab 5: Sequential Logic
Overview
Now that we have mastered combinational logic, it is time to figure out sequential circuits. In this lab, you will first play with a pre-made finite state machine (FSM) design before designing your own circuit.
Instructions
Task 1 – Mapping Sequential Logic to the FPGA
To understand the sequential logic design, simulation, and execution process we'll use a state machine that has one input w and one output out. The output is true whenever w has been true for the previous two clock cycles (i.e., it recognizes the input sequence 1,1). The SystemVerilog code for the machine is given in simpleFSM.sv (code).
Simulation
To simulate this logic, we not only have to provide the inputs, but must also specify the clock. For that, we can embed some extra logic in the test bench. The test bench for this FSM is found in simpleFSM_tb.sv (code). Simulate the design with ModelSim, and make sure that it works as you expect.
Clocks are really important to FSMs, so it is useful to set ther grey gridlines in the Wave pane to line up with the positive edger of the clocks. Click on the "Edit Grid & Timeline Properties…" icon in the lower-left corner of the Wave pane:
Set the "Grid Period" to 100 ps, which is the simulation clock period (set by parameter CLK_PERIOD = 100;), and the grid lines will line up with the clock. Make sure to save the formatting to the simpleFSM_wave.do file!
Hardware Implementation
To set up the design to run on the FPGA, we need to connect a (real) clock to the circuit, but the clocks on the chip are very fast (50 MHz is a clock cycle every 20 ns). We'd like to use a slower clock, so we provide a clock divider – a circuit that generates slower clocks from a master clock. DE1_SoC.sv (code) is a top-level module that includes a clock divider defined in clock_divider.sv (code) and sets up simpleFSM to use the LEDs and push buttons.
whichClock=25 yields a clock frequency of 0.75 Hz → a clock cycle every 1.33 seconds.
Add the new DE1_SoC.sv and clock_divider.sv to your project, compile the design for the FPGA, and test it on the DE1. This design uses KEY0 for reset (i.e., press to reset the circuit) and KEY1 as the w input. LEDR5 shows the clock, LEDR3 shows the reset, and LEDR0 shows the output of the FSM.
You do not have to demonstrate this circuit working, but running this test will help a LOT in getting the design problem working.
Task 2 – Runway Landing Lights
The landing lights at the local airport SEA-TAC are busted, so we have to come up with a new set. In order to show pilots the wind direction across the runways, we will build special wind indicators to put at the ends of all runways at SEA-TAC.
Your circuit will be given two inputs (SW[1] and SW[0]), which indicate wind direction, and three output LEDs (LEDR[2:0]) to display the corresponding sequence of lights:
P1: 0 1 0
P1: 0 1 0
P2: 1 0 0
P1: 0 1 0
P2: 0 0 1
For each situation, the lights should cycle through the given pattern. In a "Calm" wind, the lights will cycle between the outside lights lit, and the center light lit (two patterns), over and over again. The "Right to Left" and "Left to Right" crosswind indicators repeatedly cycle through three patterns each, which makes the light "move" from right to left or left to right, respectively.
The switches should never both be True. The switches may be changed at any point during the current cycling of the lights, and the lights must switch over to the new pattern as soon as possible. However, it can enter into any point in the other situation's pattern.
Design your own FSM to implement the runway landings lights described above, test it thoroughly, and make sure it runs correctly on the DE1. Make sure you include a reset button. Think carefully about your FSM design! This can be accomplished using 4 states.
Lab Requirements
Lab Report
Due before Wednesday section, submitted as a PDF on .
- A drawing of your Finite State Machine.
- A screenshot of the ModelSim simulations you will demonstrate during the demo.
- A screenshot of the "Resource Utilization by Entity" page, showing your design's computed size.
- How many hours (estimated) it took to complete this lab in total, including reading, planning, designing, coding, debugging, and testing.
- Separately, upload the SystemVerilog code for your runway lights design and related test bench(es).
Lab Demo
Due by the end of the day on Friday, but typically during your assigned demo slot or a scheduled support hour.
- Demonstrate your runway lights circuit working in simulation.
- Demonstrate your runway lights circuit working on the DE1 board.
- Be prepared to answer questions on both the theoretical and practical parts of the lab.
Grading
Working Design
100 points for correctness, style, and testing.
Bonus
10 points for developing the smallest circuit possible, in terms of number of FPGA logic and DFF resources.
To compute the size of your FSM, compile your design in Quartus and look at the Compilation Report (Figure below). In the left-hand column, select "Analysis & Synthesis" → "Resource Utilization by Entity." The "Combinational ALUTs" column lists the # of FPGA logic elements being used, and the "Dedicated Logic Registers" is the # of DFFs used.
For each entry there is the listing of the amount of resources used by that specific module (the number in parentheses), and the amount of resources used by that specific module plus its submodules (the number outside the parentheses).
Add the numbers outside the parentheses for the entire design under "Combinational ALUTs" and "Dedicated Logic Registers." Subtract from that the same numbers from the "clock_divider" line. The simpleFSM from the first part of this lab has a score of (28+28)-(26+26) = 4, though obviously it doesn't perform the right functions for the runway lights…