// 2:1 multiplexer built on top of AOI module
module MUX2 (V, SEL, I, J);
   output logic V;
   input  logic SEL, I, J;
   logic  SELN, VN;

   not G1 (SELN, SEL);
   AOI G2 (.F(VN), .A(I), .B(SEL), .C(SELN), .D(J));
   not G3 (V, VN);

endmodule  // MUX2