// Test bench for string_lights module
module string_lights_tb ();
  // signal declarations
  logic [9:0] LEDR;
  logic [3:0] KEY;
  logic [9:0] SW;

  // module instantiation
  string_lights dut (.*);

  // clock generation
  parameter T = 100;
  initial
    KEY[0] = 1'b1;
  always begin
    #(T/2)  KEY[0] <= 1'b0;
    #(T/2)  KEY[0] <= 1'b1;
  end

  // test vectors
  initial begin
    SW[0] <= 1'b0; SW[9] <= 1'b1; @(negedge KEY[0]);  // reset
    SW[0] <= 1'b0; SW[9] <= 1'b0; @(negedge KEY[0]);  // 0
    SW[0] <= 1'b1;                @(negedge KEY[0]);  // 1
    SW[0] <= 1'b0;                @(negedge KEY[0]);  // 0
    SW[0] <= 1'b0;                @(negedge KEY[0]);  // 0
    SW[0] <= 1'b1;                @(negedge KEY[0]);  // 1
    SW[0] <= 1'b1;                @(negedge KEY[0]);  // 1
    SW[0] <= 1'b0;                @(negedge KEY[0]);  // 0
    SW[0] <= 1'b0;                @(negedge KEY[0]);  // 0
    SW[0] <= 1'b0;                @(negedge KEY[0]);  // 0
    SW[0] <= 1'b1;                @(negedge KEY[0]);  // 1
    SW[0] <= 1'b1;                @(negedge KEY[0]);  // 1
    SW[0] <= 1'b1;                @(negedge KEY[0]);  // 1
                                  @(negedge KEY[0]);  // final delay
    $stop;
  end

endmodule  // string_lights_tb