module countRight (
	input logic clk, rst, correct, submit,
	output logic next, psychic
	); 
	
	logic [3:0] count_correct; // intermidate signal to count the correct guess
	
	enum logic [2:0] {init, wrong_guess, correct_guess, idle } ps, ns;
	
	always_ff @(posedge clk) begin
		if (rst)
			ps <= init;
		else 
			ps <= ns;
	end
	
	assign ns = ~submit ? idle : (correct ? correct_guess : wrong_guess);
	assign next = (ps == init || ps == idle) ? 0 : 1;
	always_ff@(posedge clk)
		case (ps)
        init: begin
            count_correct <= 4'b0000;   
        end
		  
        wrong_guess: begin
            count_correct <= 4'b0000;
        end
		  
        correct_guess: begin
            count_correct <= count_correct + 1; 
        end
		  
		  idle: begin
				count_correct <= count_correct;  
		  end
		  
        default: begin
            count_correct <= count_correct;
        end
		  
    endcase			
	
	assign psychic = ~|(count_correct ^ 4'b1000); 
	
 endmodule  // countRight
 
 
module countRight_tb ();
	
	logic clk, rst, submit, correct , next, psychic;
	
	countRight dut (.*);
	
	parameter T = 100;
   initial
		clk = 1'b0;
	always begin
		#(T/2)  clk <= 1'b0;
		#(T/2)  clk <= 1'b1;
	end
	
	initial begin
		rst <= 1; @(posedge clk); 
		rst <= 0; submit <= 1; correct <= 0;  @(posedge clk); 
		submit <= 0; correct <= 0;@(posedge clk); 
	   submit <= 0; correct <= 1;@(posedge clk); 
	   submit <= 1; @(posedge clk); 
		correct <= 1;@(posedge clk); 
		@(posedge clk); 
		@(posedge clk); 
		@(posedge clk); 
		@(posedge clk);
	   submit <= 0; correct <=0;	
		@(posedge clk); 
		@(posedge clk);
	   submit <= 1; correct <=1;	
		@(posedge clk); 
		@(posedge clk);
	   submit <= 1; correct <=0;	
		@(posedge clk); 
		@(posedge clk);
		
	   	
		
	
		$stop;
	end
	
	

	
endmodule  // countRight_tb