module userIn (
	input logic [3:0] guess_ext, 
	input logic clk, rst, submit_ext, 
	output logic [3:0] guess,
	output logic submit
	);
	
	// intermidate signals 
	logic submit_sync;
	logic [3:0] guess_sync;
	
	// instantiate synchronizer for inputs except reset
	synch g0(.clk, .reset(rst), .in(guess_ext[0]), .out(guess_sync[0]));
	synch g1(.clk, .reset(rst), .in(guess_ext[1]), .out(guess_sync[1]));
	synch g2(.clk, .reset(rst), .in(guess_ext[2]), .out(guess_sync[2]));
	synch g3(.clk, .reset(rst), .in(guess_ext[3]), .out(guess_sync[3]));
	synch s_synch(.clk, .reset(rst), .in(submit_ext), .out(submit_sync));
	
	assign guess = guess_sync;
	
	// instantiate edge detector for KEY inputs except reset
	pulse s_pulse(.clk, .reset(rst), .in(submit_sync), .out(submit));
	

endmodule  // userIn


module userIn_tb ();
	logic clk, rst, submit_ext;
	logic [3:0] guess_ext;
	logic [3:0] guess;
	logic submit;
	userIn dut (.*);
	
	// set up the clock
	parameter CLOCK_PERIOD = 100;
	initial begin
		clk <= 0;
	   forever #(CLOCK_PERIOD/2) clk <= ~clk;
	end
	
	// Set up the inputs to the design. Each line is a clock cycle.
   initial begin
    // Defining ALL input signals at t = 0 will avoid red (undefined) signals
    // in your simulation.
		guess_ext <= 4'b0000;	    rst <= 1;  submit_ext <= 0 ; 
	 @(posedge clk);  rst <= 0;    submit_ext <= 1 ; 
    @(posedge clk);               submit_ext <= 0 ;          
    @(posedge clk);                          
    @(posedge clk);               
	 @(posedge clk);               submit_ext <= 1;          
	 @(posedge clk);                          
	 @(posedge clk);              
	 @(posedge clk);
	 @(posedge clk); rst <= 1;
	 @(posedge clk); rst <= 0;     submit_ext <= 0; 
	 @(posedge clk);              
	 @(posedge clk);
	 @(posedge clk);              
	        
    $stop;  // pause the simulation
  end
endmodule  // userIn_tb