Syllabus

Course Goals

This course introduces students to the basic components and techniques that underpin digital circuits, starting from logic gates and building towards larger building blocks such as adders and finite state machines (FSMs). This course emphasizes simulation in SystemVerilog and implementation on field-programmable gate arrays (FPGAs). This is the introductory course for computer engineering; related courses of particular interest include:


Topic List

  • Combinational logic: logic gates, Boolean algebra
  • Logic simplification: Karnaugh maps
  • Sequential logic: flip-flops, registers
  • Timing considerations
  • Finite state machines (FSMs)
  • Routing elements and adders
  • Shift registers and counters
  • SystemVerilog

Course Components

The course consists of the following elements:

  • Lectures: There will be 10 lectures. In-person attendance is highly encouraged, but slide PDFs and recordings will be made available afterward.
  • Labs and Lab Demos: There are 6 one-week labs followed by a two-week final lab/project. These assignments will reinforce the practical aspects of digital design implementation and SystemVerilog coding skills.
    • We will distribute a lab kit that includes the .
    • The necessary software can be accessed in the lab space (CSE 003) or installed on your local machine.
  • Quizzes: There will 3 in-class quizzes throughout the quarter – see the for more information. There is no midterm or final exam. These will reinfornce the conceptual and theoretical aspects of digital design covered in the course.
  • Optional Readings: The optional text is the third edition of Brown and Vranesic's Fundamentals of Digital Logic with Verilog Design book ("B&V"), ISBN 9870073380544. The readings are listed on the course schedule.

Policies

Grading Policies

We will compute your course grade as follows:

  • Labs: 66%
  • Quiz 1: 10%
  • Quiz 2: 10%
  • Quiz 3: 14%

We will use a straight-scale grading system with linear interpolation. Extra credit opportunities will be factored directly into your grades (i.e., 1 extra credit point = 1 normal point).

  • 95% → 4.0, 87.5% → 3.5, 80% → 3.0, 72.5% → 2.5, 65% → 2.0

Lab Policies

Labs are a combination of a lab report and a lab demo, which are graded independently:

  • The lab reports are submitted to and are due Wednesday @ 2:30 pm, which is before you demo with a TA. This is to encourage you to do all of your testing and data collection as you develop your lab and will prepare you for the lab demo.
  • The lab demos are done synchronously with a TA, typically during your assigned 10-minute lab demo slot on Wednesday or Thursday afternoon.
    • Lab demos are a chance for you to present your work and get feedback as you get more comfortable with SystemVerilog and the DE1-SoC. The TAs will also have 1-2 short questions for you to answer about the lab.
    • It is possible to get a full demo score even if you do not finish the lab! Please come and present what work you did and where/how you got stuck so the TAs can give you feedback and tips for future labs.

Late Policy

Lateness applies differently to the lab reports and the lab demos:

  • Lab reports have lateness counted in days after the Wednesday 2:30 pm deadline.
    • No lab report may be submitted more than 2 days late (i.e., final deadline is Friday @ 2:30 pm).
    • You will be given 4 late day tokens for the quarter that will cancel out penalties for late submissions. Once you have exhausted your late day tokens, each remaining late day will become a 10% penalty assessed on one of your late submissions, though chosen to maximize your overall score.
    • There is no bonus for having leftover late days at the end of the quarter.
  • Lab demos cannot be penalized but must be completed by the end of Friday each week. You are allowed to demo during office hours, but should notify the course staff ahead of time (e.g., via private post on Ed) to book a 10-minute slot.
    • Unless you are submitting your lab report late, you will be expected to demo during your assigned lab demo slot each week.

Student Conduct and Academic Integrity

The University of Washington Student Conduct Code (WAC 478-121) defines prohibited academic and behavioral conduct and describes how the University holds students accountable as they pursue their academic goals. Allegations of misconduct by students may be referred to the appropriate campus office for investigation and resolution. More information can be found online at .


Disability Resources

Your experience in this class is important to us. It is the policy and practice of the University of Washington to create inclusive and accessible learning environments consistent with federal and state law. If you have already established accommodations with , please activate your accommodations via myDRS so we can discuss how they will be implemented in this course.

If you have not yet established services through DRS, but have a temporary health condition or permanent disability that requires accommodations (conditions include but not limited to; mental health, attention-related, learning, vision, hearing, physical or health impacts), contact DRS directly to set up an Access Plan. DRS facilitates the interactive process that establishes reasonable accommodations. Browse to to start the process as soon as possible to avoid delays.

You can refer to the university policies regarding for more information.


Religious Accommodations

Washington state law requires that UW develop a policy for accommodation of student absences or significant hardship due to reasons of faith or conscience, or for organized religious activities. The UW's policy, including more information about how to request an accommodation, is available at . Accommodations must be requested within the first two weeks of this course using the .


Extenuating Circumstances and Inclusiveness

We recognize that our students come from varied backgrounds and can have widely-varying circumstances. If you have any unforeseen or extenuating circumstance that arise during the course, please do not hesitate to contact the instructor in support hours, via email, or private Ed Discussion post to discuss your situation. The sooner we are made aware, the more easily these situations can be resolved. Extenuating circumstances include work-school balance, familial responsibilities, military duties, unexpected travel, or anything else beyond your control that may negatively impact your performance in the class.

Additionally, if at any point you are made to feel uncomfortable, disrespected, or excluded by a staff member or fellow student, please report the incident so that we may address the issue and maintain a supportive and inclusive learning environment. Should you feel uncomfortable bringing up an issue with a staff member directly, you may consider sending or contacting the .