EE/CSE 371 Sp23: Design Of Digital Circuits And Systems

Course Staff

	Photo	Name	E-mail	Photo	Name	E-mail
Instructor		Justin Hsia	jhsia@cs
Teaching Assistants		Jared Yoder	jmyoder		Kaamakshee M P	kshee97
		Matt Guo	mguo5		Patrick Ho	pyho
		Robert Crist	rcrist		Sanjukta Roychoudhury	sroyc

Course questions should be brought to office hours or posted on the course discussion board; questions will not be answered through emails.  Please limit emailing the course staff to personal issues and other extenuating circumstances (see bottom of this page).

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Scheduled Sections

	Location	Times	Staff Members
Lecture	SMI 120	TuTh 10:30 am - 12:20 pm	Justin + TAs
Labs	ECE 365 / Zoom	Th 12:30 - 3:30 pm Th 3:30 - 6:30 pm F 12:30 - 3:30 pm	Matt, Kaamakshee Patrick, Jared Sanjukta, Robert
Other Office Hours	ECE 365 / Zoom (H) = hybrid (P) = in-person (Z) = Zoom	M 4:30 - 6:30 pm (H) Tu 12:30 - 2:30 pm (H) Tu 4:00 - 6:30 pm (H) W 12:30 - 3:20 pm (H) W 4:30 - 5:30 pm (H) See Zoom tab or Canvas Calendar. Please use the Office Hour Queue.	Matt, Robert Matt, Sanj, Kaam Jared, Sanj, Kaam Patrick, Justin (Z) Robert, Jared

Note: If you forget when your scheduled demonstration time slot is, please see the comments on the "Lab Demo Slot" assignment.

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Class Schedule

Lecture Topics:

1. EDA tools and SystemVerilog
2. Finite State Machines (Mealy and Moore)
3. Memories: ROM, RAM, register files, FIFO buffers
4. Algorithmic State Machine (ASM) charts plus Datapath (ASMD)
5. Algorithms to hardware/datapath
6. Timing: static timing analysis, clock domain crossing, pipelining
7. Communication
8. Advanced Testing: assertions, classes, randomization

Tentative Schedule:  (subject to change)

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Course Materials

• This Canvas site will have lecture slides and lab assignments posted in the Files section as we go.  Submit your homework answers and lab materials to Gradescope.
• We will be using Ed Discussion for our Discussion Board.  Announcements will also be made here, so make sure you enroll.
• We will be using SystemVerilog to design our circuits and systems.  The simulation tool Quartus 17.0 will be used for simulating and synthesizing designs.  
• For labs, we will access the DE1-SoC Development Kit remotely via the LabsLand web interface.
• There is no required textbook.
• Resources:
  • Information for Assignments (pdf)
  • LabsLand Setup (pdf)
  • Quartus 17.0 Install Files:  (dir)
  • Installing Quartus (pdf)
  • SystemVerilog Quick Reference Card:  (pdf)
  • SystemVerilog Tutorial:  (pdf)
  • SystemVerilog Common Issues:  (Google Doc)
  • ModelSim Usage Guide:  (Google Doc)
  • GPIO Guide (pdf, sv, tb)
  • Peripheral drivers (dir)
  • Reference Material for DE1-SoC, SystemVerilog, and ModelSim (dir)

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Grading

Category	Homework	Labs	Quizzes
% of Grade	20%	50%	30%

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Assignment Policies

• This course is about design, which is inherently a creative endeavor.  Therefore, you should expect some vagueness in the lab specs.  If a particular detail is missing from the spec, it is left up to you to decide and define how you will go about it.  The TAs will be happy to assist you, however, it is expected that YOU are the one who comes up with your approach and final design and that you are able to describe and defend your choices during lab demos.
• Debugging is often time-consuming and frustrating, but it is one of the most important skills to develop.  TAs will provide guidance but will not fully debug your programs.
  • Simulations are an important tool to help you debug your programs, so you should expect to use test benches and ModelSim extensively in this course.
• There are 6 homework:  all can be (optionally) completed in groups of up to 4 students.  This is to encourage you to interact with your peers and to help you work through your gaps in understanding and misconceptions.  Homework give you additional practice with the course concepts and programming in SystemVerilog and are intended to set you up for success for the labs and quizzes.
• There are 6 labs, which can be (optionally) completed with a partner; you may change partners in-between labs.  Labs are a combination of a lab report and a lab demo, which are graded independently:
  • The lab reports are submitted to Gradescope and are due Wednesday @ 11:59 pm, which is before you demo with a TA.  This is to encourage you to do all of your testing and data collection as you develop your lab and will prepare you for the lab demo.
    • See the Lab Report Example for a sense of what you will be asked to do.
  • The lab demos are done synchronously with a TA, typically during your assigned 15-minute lab demo slot on Thursday or Friday.
    • Lab demos are a chance for you to present your work and get feedback as you get more comfortable with SystemVerilog and the DE1-SoC.  The TAs will also have 1-2 short questions for you to answer about the lab.
    • It is possible to get a full demo score even if you do not finish the lab!  Please come and present what work you did and where/how you got stuck so the TAs can give you feedback and tips for future labs.
    • Missing a lab demo will result in a zero grade for the entire lab; when working in a partnership, both partners must be present in order to demo.  We reserve the right to adjust grading based on individual contributions to the partnership.

Late Policies

• You are expected to submit your assignments by the due date and we highly recommend starting early in order to give yourself sufficient time to seek out assistance as necessary and complete them.
• Homework cannot be submitted late because we will release solutions immediately to help you prepare for the quizzes.
• Lab reports have lateness counted in days after the Wednesday 11:59 pm deadline.
  • No lab report may be submitted more than 2 days late (i.e., final deadline is Friday @ 11:59 pm).
  • You will be given 5 late day tokens for the quarter that will cancel out penalties for late submissions.  Once you have exhausted your late day tokens, each remaining late day will become a 10% penalty assessed on one of your late submissions, though chosen to maximize your overall score.
• Lab demos can only be done after submitting the associated lab report.  These cannot be penalized but must be done within a week of the lab report due date.  You will have an assigned demo slot, but you can also arrange to demo at the staff's discretion at a different time if needed (e.g., during an office hour if you submit the lab report late).  Drop-in lab demos are not allowed; please contact us ahead of time.
  • Unless you are submitting your lab report late, you will be expected to demo during your assigned lab demo slot each week.

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Collaboration Policies and Tips

We are actively encouraging collaboration this quarter (everything but the quizzes) – this can help you manage the workload better and make your experience in the class more enjoyable.  However, working with a partner does NOT automatically guarantee a smoother and easier workflow!  A common misconception is that working with a partner means that your workload gets cut in half.  This won't be the case, but that's okay!  If each of your workloads ends up at less than what it would have been working individually, then that's a win! The main benefit of working with partners is the ability to discuss your approach and share code without worrying about violating any academic conduct rules.  For 371, in particular, some major gains should be in the reduction of debugging time and having others generate figures and proofread lab reports.

Effective collaboration always involves frequent communication!  This could be working side-by-side synchronously or having frequent check-ins with your partners, but a complete division of labor (e.g., I'll handle this part and you do this part now go) without checking-in is a recipe for disaster, as you still end up working alone without support and also miss out on the learning gains from the parts that you don't do!

Group Submissions

All assignment submissions (except for quizzes) will be submitted via Gradescope.

• Only submit the requested files!  In particular, project build files from Quartus clutter up the grading interface and can cause your submission upload to fail.  In general, you will only be submitting PDF and SV files.
• Only 1 group member should submit to Gradescope and then add their partners afterward using the "+ Add Group Member" link:
  
  
  • Note that the partnerships apply per submission, so if you resubmit a newer version of the assignment later, you will again need to add your groupmates to the submission.

GitLab Repo Sharing

You will be given a Gitlab repo for the quarter to better enable collaboration (it beats emailing project files back and forth!).  If you are less familiar with git, don't hesitate to ask a staff member or view the following resources:

• CSE 333 GitLab guide
• git tutorial
• git book

To Add Your Partner to Your Repo:

1. Log on to the Gitlab web interface and navigate to your repo for EE/CSE 371. On the left menu, hover over "Project information" and then click on "Members".
2. In the "GitLab member or Email address" box, type in your partner's netid and then select the "Maintainer" role.
3. Click the "Invite" button and you should be ready to go!

To Remove a Partner from Your Repo:

1. Log on to the Gitlab web interface and navigate to your repo for EE/CSE 371. On the left menu, hover over "Project information" and then click on "Members".
2. Scroll down to find your former partner's name and then click the red trash can button in their row.

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Academic Integrity and Conduct

There is a very fine line between collaboration and cheating.  We can learn a lot from working with each other and it can make the course more enjoyable, but we also want to ensure that every student can get the maximum benefit from the material this course has to offer.  Keep in mind that the overall goal is for *YOU* to learn the material so you will be prepared for job interviews, projects, etc. in the future.  Cheating turns the assignments into an exercise that is a silly waste of both your time and ours; save us both by not doing it.

Cheating consists of sharing code or solutions to assignments by either copying, retyping, looking at, or supplying a copy of a diagram or file.  Examples include:

• Coaching a friend to arrive at a solution by simply following your instructions (i.e., no thinking involved). An example is helping a friend write a program line-by-line.
• Copying code from a similar course at another university or using solutions/code on the web, including GitHub, Chegg, and AI generative tools like ChatGPT.
• Communicating your solution with another student via electronic or non-electronic means.

Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade on the assignment and the initiation of a cheating case in the University system.  Cheating is an insult to the instructor and course staff, to the department and major program, and most importantly, to you and your fellow students.  If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor.  Just don't cheat.  If you are in doubt about what might constitute cheating, send the instructor an email describing the situation and we will be happy to clarify it for you.

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Disability Resources

The Disability Resources for Students (DRS) is a unit within the Division of Student Life and is dedicated to ensuring access and inclusion for all students with disabilities on the Seattle campus. They offer a wide range of services for students with disabilities that are individually designed and remove the need to reveal sensitive medical information to the course staff. If you have a medical need for extensions of exam times or assignment deadlines, these will only be granted through official documentation from DRS. Navigate to this link to start the process as soon as possible to avoid delays.

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Religious Accommodations

Washington state law requires that UW develop a policy for accommodation of student absences or significant hardship due to reasons of faith or conscience, or for organized religious activities. The UW’s policy, including more information about how to request an accommodation, is available at Religious Accommodations Policy. Accommodations must be requested within the first two weeks of this course using the Religious Accommodations Request form.

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Extenuating Circumstances

We recognize that our students come from varied backgrounds and can have widely-varying circumstances. If you have any unforeseen or extenuating circumstances that arise during the course, please do not hesitate to contact the instructor in office hours, via email, or private Ed Discussion post to discuss your situation. The sooner we are made aware, the more easily these situations can be resolved. Extenuating circumstances include work-school balance, familial responsibilities, religious observations, military duties, unexpected travel, or anything else beyond your control that may negatively impact your performance in the class.

Additionally, if at any point you are made to feel uncomfortable, disrespected, or excluded by a staff member or fellow student, please report the incident so that we may address the issue and maintain a supportive and inclusive learning environment. Should you feel uncomfortable bringing up an issue with a staff member directly, you may consider sending anonymous feedback or contacting the Office of the Ombud.

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