Course Calendar     CSE 467    Winter, 2005

Week Monday Wednesday Friday

1
Lab 1

1/3 Introduction & Class Overview
1/5

FPGA origins

1/7

Review: Combinational Logic
Homework 1 Assigned

2
Lab 2
1/10

Review: Clocking & Synchronous Circuit Model
Reading: virtex datasheet; verilog manual

1/12

Review: Clocking & Synchronous Circuit Model
Problem of the Week due

1/14 Lab 3 SRAMs
Homework 1 due; quiz
3
Lab3
1/17

Holiday
MLK Day

1/19 Review: Finite State Machines
1/21

Combinational Verilog; FSMs & Sequential Verilog
Homework 2 due

4
Lab4
Scope tutorial

1/24

IP and Microblaze
Reading: Introduction to Microblaze

1/26 Audio Basics and Digital Synthesis
Reading: EDK intro and EST intro
1/28

more audio
homework 3 due; Problem of the Week due
Reading:
IP guide and Drivers guide

5
Lab 5
1/31

Logic Analyzers
Reading:
OPB EMC datasheet

2/2

Physical Modeling Synthesis ;quiz
Reading: waveguide paper

2/4 Physical Modeling Synthesis
Bowl movie
6
Lab 6
2/7

Intro to Digital Filters

2/9

Guest Lecture: Carl Ebeling
Parallel Prefix Computation-Fast Addition

2/11

Pipelining
homework 4 due

7
Lab 7
Parts 1&2

2/14

Retiming/ C-Slowing

2/16 Guest Lecture: Carl Ebeling
More on Parallel Prefix Computation
2/18

Electrical Realities; quiz

8
Lab 7
Parts 3&4

2/21

Holiday
Presidents Day

2/23

Waveguide Instruments

2/25 Overview of FPGA Architectures
Homework 5 due

9
Final Project

2/28 Notes on final project
3/2

Bill Baxter, guest

3/4

Register Timing Model/ Clock Skew

10
Final Project

3/7 FPGA Design tips ; quiz 3/9

CMOS; Fabrication -- Charlie Giefer
Homework 6 due

3/11 Summary & Review; sign-up for Project Demo times
Final Exam Study Guide
Thursday, 3/17: Final Exam 8:30-10:20 a.m.
Comments to: bruceh@cs