Draw the cache tables and the state of all bits within them. Suppose you have a 16 byte cache with 2 byte long cachelines that is 2-way set associative and write-back. Further assume that prior to processing any read/write requests the state of memory is M[a] = a, or another words, the byte at address 0 is 0, address 1 is 1, address 2 is 2, and so on. Assume an *8 bit* long address. Along with depicting the cache tables, please answer the following questions:

How many bits are devoted to the line size?

How many bits are devoted to the index?

How many bits are devoted to the tag?

Here is the sequnce of read/write requests:

    Read 0x01
    Read 0x02
    Read 0x03
    Write 0x05, Value=100
    Write 0x06, Value=101
    Write 0x07, Value=102
    Write 0x06, Value=103
    Read 0x03
    Read 0x07
    Read 0x01
    Read 0x02
    Read 0x03

How accesses to the cache hit?

How many accesses missed?

How many times did the cache write values back to main memory?