Contact
ebeling
cs.washington.edu
cs.washington.eduAreas of interest: Architecture, design and implementation of hardware systems, especially reconfigurable platforms
Crunching large graphs with commodity processors
, Proceedings of the 3rd USENIX conference on Hot topic in parallelism, USENIX Association, 2011.
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array
, Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, 2011.
A Model for Programming Large-Scale Configurable Computing Applications'
, First Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, 2010.
Managing short versus long lived signals in Coarse-Grained Reconfigurable Arrays
, International Conference on Field-Programmable Logic and Applications, IEEE, 2010.
SPR: an architecture-adaptive CGRA mapping tool
, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM, 2009.
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
, International Conference on Field-Programmable Logic and Applications, 2009.
Macah: A C-Level Language for Programming Kernels on Coprocessor Accelerators
, University of Washington, Department of CSE, 2008.
Implementing Molecular Dynamics simulation using the Hybrid Micro-Parallel model
, Submitted to IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE, 2007.
Macah: A "C-Level" Programming Language for Kernel Acceleration on Hybrid Micro-Parallel Architectures
, Submitted to LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Language, Compilers and Tool Support for Embedded Systems, ACM Press, 2007.
Abstract Verilog: A Hardware Description Language for Novice Students
, International Symposium on Microelectronics Systems Education, IEEE Computer Society, 2007.
Configurable Computing Platforms - Promises, Promises
, IEEE 17th International Conference on Application-Specific System, Architectures and Processors (ASAP 2006), 2006.
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
, Proceedings of the International Conference on Field Programmable Logic and Applications, 2006.
<p>Best paper award for FPGA technology.</p>
A Type Architecture for Hybrid Micro-Parallel Computers
, IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE, 2006.
PipeRoute: a pipelining-aware router for reconfigurable architectures
, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25:3, 2006.
Architecture-adaptive routability-driven placement for FPGAs
, International Conference on Field Programmable Logic and Applications, 2005.
Fine-Grained Parallel Processor for Fast Cell Simulations
, Science, 2004.
QuickRoute: a fast routing algorithm for pipelined architectures
, IEEE International Conference on Field-Programmable Technology, 2004.
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
, IEEE Transactions on Computing: Special Issue on Programmable Logic and Applications, 2004.
Exploration of Pipelined FPGA Interconnect Structures
, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2004.
A Compiled Accelerator for Biological Cell Signalling Simulations
, Twelfth International Symposium on Field Programmable Gate Arrays (FPGA04), 2004.
PipeRoute: A pipelining-aware router for FPGAs
, Symposium on Field Programmable Gate Arrays (FPGA03), ACM Press, 2003.
<p>New York</p>
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
, International Conference on Field-Programmable Logic and Applications, Springer, 2003.
Compiling to Coarse-Grained Adaptable Architectures
, University of Washington Technical Report:UW-CSE-02-06-01, 2002.
An Emulator for Exploring RaPiD Configurable Computing Architectures
, International Conference on Field-Programmable Logic and Applications, Springer-Verlag, 2001.
<p>Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA</p>
Distributed-memory parallel routing for field-programmable gate arrays
, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19:8, 2000.
Architecture design of reconfigurable pipelined datapaths
, Advanced Research in VLSI, 1999. Proceedings. 20th Anniversary Conference on, 1999.
Using precomputation in architecture and logic resynthesis
, IEEE/ACM International Conference on Computer Aided Design, ACM Press, 1998.
<p>San Jose, California, United States</p>
Specifying and Compiling Applications for RaPiD
, IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 1998.
Mesh routing topologies for multi-FPGA systems
, IEEE Transactions on VLSI Systems 6:3, 1998.
An Overview of Prediction-Based Architectural Retiming
, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-97), 1997.
Experiments in the Iterative Application of Resynthesis and Retiming
, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-97), 1997.
Sequential Logic Synthesis using Precomputation
, International Workshop on Logic Synthesis (IWLS-97), 1997.
Whither configurable computing?
, The Thirtieth Hawaii International Conference on System Sciences 1, 1997.
Mapping applications to the RaPiD configurable architecture
, IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 1997.
ChaosLAN: Design and implementation of a gigabit LAN using chaotic routing
, Proceedings of the Workshop on Parallel Computer Routing and Communication, 1997.
Configurable computing: the catalyst for high-performance architectures
, IEEE International Conference on Application-Specific Systems, Architectures and Processors, 1997.
Experiences with the MacTester in computer science and engineering education
, IEEE Transactions on Education 40:1, 1997.
Seeking Solutions in Configurable Computing
, Computer, IEEE Computer Society 30, 1997.
RaPiD - Reconfigurable Pipelined Datapath
, International Workshop on Field-Programmable Logic and Applications, Springer-Verlag, Berlin, 1996.
Architectural retiming: pipelining latency-constrained circuits
, 33rd annual conference on Design automation conference, ACM Press, 1996.
<p>Las Vegas, Nevada, United States</p>
The Triptych FPGA architecture
, IEEE Transactions on Very Large Scale Integration Systems 3:4, 1995.
PathFinder: A negotiation-based performance-driven router for FPGAs
, ACM International Symposium on Field-Programmable Gate Arrays, ACM Press, 1995.
<p>Monterey, California, United States</p>
Placement and routing tools for the Triptych FPGA
, IEEE Transactions on VLSI Systems 3:4, 1995.
On the performance of level-clocked circuits
, Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on, 1995.
Architectural Retiming: An Overview
, TAU, 1995.
Mesh Routing Topologies for FPGA Arrays
, ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, 1994.
Springbok: A Rapid-Prototyping System for Board-Level Design
, International Workshop on Field-Programmable Gate Arrays, 1994.
Optimal retiming of level-clocked circuits using symmetric clock schedules
, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13:9, 1994.
Mesh routing topologies for multi-FPGA systems
, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994.
An FPGA for implementing asynchronous circuits
, IEEE Design & Test of Computers 11:3, 1994.
CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks
, Proceedings of the First International Workshop on Parallel Computer Routing and Communication, PCRCW'94, 1994.
The Chaos Router Chip: Design and Implementation of an Adaptive Router
, Proceedings of the IFIP Conference on VLSI (VLSI-93), 1993.
Minimizing the Effect of Clock Skew Via Circuit Retiming
, Proceedings of TAU'93: 1993 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1993.
The practical application of retiming to the design of high-performance systems
, IEEE/ACM International Conference on Computer Aided Design, IEEE Computer Society Press, 1993.
<p>Santa Clara, California, United States</p>
SubGemini: Identifying subcircuits using a fast subgraph isomorphism algorithm
, International on Design Automation Conference, ACM Press, 1993.
<p>Dallas, Texas, United States</p>
Routing-directed Placement for the Triptych FPGA
, ACM/SIGDA Workshop on Field-Programmable Gate Arrays, 1992.
Practical Issues in Retiming Latch-Based Circuits
, University of Washington Technical Report:CSE-TR-92-10-07, 1992.
TRIPTYCH: An FPGA Architecture with Integrated Logic and Routing
, Proceedings of the Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, 1992.
Optimal Retiming of Multi-Phase Level-Clocked Circuits
, Proceedings of the Conference on Advanced Research in VLSI., 1992.
MONTAGE: An FPGA for Synchronous and Asynchronous Circuits
, International Workshop on Field-Programmable Logic and Applications, Springer-Verlag, Berlin, 1992.
Teaching Design with a Next-Generation Schematic Capture System
, Proceedings of the Microelectronics Systems Education Conference, 1991.
Establishing a Modern Digital Design Laboratory
, Proceedings of the Microelectronics Systems Education Conference, 1991.
Rapid Low-Cost Display of Spline Surfaces
, Proceedings of the Conference on Advanced Research in VLSI, The MIT Press, 1991.
TRIPTYCH: a New FPGA Architecture
, International Symposium on FPGAs, Abingdon, England, 1991.
MacTester: A Low-Cost Functional Tester for Interactive Testing and Debugging
, Proceedings of the 1990 Microelectronic Systems Education Conference, 1990.
Making the Most of a Design Project
, Proceedings of the 1990 Microelectronic Systems Education Conference, 1990.
Computers, Chess, and Cognition
, Springer-Verlag, 1990.
A One-Year Graduate Course Sequence in VLSI Design and CAD
, Proceedings of the 1989 VLSI Education Conference, 1989.
Apex: Two Architectures for Generating Parametric Curves and Surfaces
, The Visual Computer 5:3, 1989.
Measuring the Performance Potential of Chess Programs
, Artificial Intelligence 43:1, 1989.
<p>An earlier version appeared in Advances in Computer Chess 5, Elsevier Science Publishing Co., 1989.</p>
Pattern Knowledge and Search: The SUPREM Architecture
, Artificial Intelligence 38:2, 1989.
WireLisp: combining graphics and procedures in a circuit specification language
, IEEE/ACM International Conference on Computer Aided Design, 1989.
SUPREM: An Architecture Based on Pattern Knowledge and Search
, Proceedings of the 3rd International Conference on Supercomputing, 1988.
GeminiII: a second generation layout validation program
, IEEE/ACM International Conference on Computer Aided Design, 1988.
Hardware Accelerators for Electrical CAD
, Adam Hilger, 1987.
The SUPREM Architecture: A New Intelligent Paradigm
, Artificial Intelligence 28:1, 1986.
All the Right Moves: A VLSI Architecture for Chess
, The MIT Press (ACM Distinguished Dissertation Series), 1986.
The design and implementation of a VLSI chess move generator
, International Symposium on Computer Architecture (ISCA), 1984.
Validating VLSI Circuit Layout by Wirelist Comparison
, Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD-83), 1983.
Design of a User Microprogramming Support System
, Proceedings of the 15th IEEE Computer Society Conference, 1977.