Coarse-grained reconfigurable architectures (CGRAs) have the potential to offer performance approaching an ASIC with the flexibility, within an application domain, similar to a digital signal processor. In the past, coarse-grained reconfigurable architectures have been encumbered by challenging programming models that are either too far removed from the hardware to offer reasonable performance or that bury the programmer in the minutiae of hardware specification.
This is a new project focused on models for programming large reconfigurable computing platforms. We recently presented our work at the CARL2010 Workshop held at Micro2010.
Ideally, the development phase of a new FPGA architecture would make use of a reliable set of mapping tools to produce accurate performance evaluations of proposed designs. Unfortunately, given the quick production time frames faced by most developers, tool construction is often postponed until after many architectural features have been frozen. To satisfy the need for fast tool prototyping, we have designed Emerald, a powerful architecture-driven system for quick development of FPGA tools.
Latency constraints often arise in the design of digital synchronous circuits because of cyclic dependencies and feedback paths or because of performance requirements. Ad hoc architectural modifications are typically used to improve the performance of circuits. Architectural retiming is a technique for optimizing the performance of latency-constrained circuits.
Level-clocked circuits are often used in high-performance designs because they allow delays to be shared across latches, something that is no possible with edge-triggered registers. However, retiming becomes much more difficult because of the many interacting timing constraints that must be satisfied in latch-based circuits. This research defined a new and efficient algorithm for retiming level-clocked circuits.
Triptych and Montage are FPGAs designed with integrated routing and logic, and achieve higher densities than current commercial FPGAs.
Gemini is a program that compares two circuit netlists and reports whether they are exactly the same, pinpointing differences if there are any. Gemini is typically used to determine whether a VLSI circuit layout is correct by comparing the wirelist extracted from the layout to the specification wirelist. This is also know as LVS - layout vs. schematic. Gemini is a program based on a well-known graph isomorphism algorithm that is very efficient for comparing circuits encountered in practice.