Architecture design of reconfigurable pipelined datapaths

<p>{T}his paper examines reconfigurable pipelined datapaths ({R}a{P}i{D}s), anew architecture style for computation-intensive applications thatbridges the cost/performance gap between general purpose and applicationspecific architectures. {R}a{P}i{D}s can provide significantly higherperformance than general purpose processors on a wide range ofapplications from the areas of video and signal processing, scientificcomputing and communications. {M}oreover, {R}a{P}i{D}s provide the flexibilitythat does not come with application-specific architectures. {A} {R}a{P}i{D}architecture is optimized for highly repetitive,computationally-intensive tasks. {V}ery deep application-specificcomputation pipelines can be configured that deliver very highperformance for a wide range of applications. {R}a{P}i{D}s achieve this usinga coarse-grained reconfigurable architecture that mixes the appropriateamount of static configuration with dynamic control. {W}e describe thefundamental features of a {R}a{P}i{D} architecture, including the linear arrayof functional units, a programmable segmented bus structure, and aprogrammable control architecture. {I}n addition, we outline the floorplanof the architecture and provide timing data for the most critical paths.{W}e conclude with performance numbers for several applications on aninstance of a {R}a{P}i{D} architecture</p>