On the performance of level-clocked circuits

<p>{A}lthough it is well-known that substituting level-sensitivelatches for edge-triggered registers can boost circuit performance,results of measuring the performance gained by using latches in realcircuits-when retiming is used to optimize the performance of both typesof circuits-have been disappointing. {I}n this paper we re-examine thespeedup that can be expected from using latches and develop upper andlower bounds on the clock period of retimed circuits that are tighterthan previously published bounds. {W}e then show experimentally thatpipelined level-clocked circuits almost always achieve the lower boundwhile edge-clocked circuits seldom do. {T}hese bounds also illuminatewhere performance from level-clocking can and cannot be achieved. {F}orthe circuits that do benefit from latches, the average speedup is about11%, although much greater speedups are common. {A}nother factor affectingperformance that has generally been ignored is clock skew. {C}locks inedge-clocked circuits must be slowed down by an amount equal to theclock skew while level-clocked circuits are more tolerant of clock skew.{W}e show experimentally that on average level-clocked circuits cantolerate clock skew of 15% of the clock period which can be translateddirectly into increased performance</p>