Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays

<p>{S}patially-tiled architectures, such as coarse-grained reconfigurable arrays ({CGRA}s), are powerful architectures for accelerating applications in the digital-signal processing, embedded, and scientific computing domains. {I}n contrast to field-programmable gate arrays ({FPGA}s), another common accelerator, they typically time-multiplex their processing elements and are word rather than bit-oriented. {T}hese differences lead us to re-examine some of the traditional architecture choices made for {FPGA}s as we move to these coarser-granularity architectures. {I}n this paper we study the efficiency of time-multiplexing global interconnect as architectures scale from single-bit to multi-bit datapaths. {U}sing the {M}osaic infrastructure, we analyzed the design trade-offs involved in static vs. time-multiplexed routing for global interconnect channels, as well as the benefit of including a dedicated bit-wide control interconnect to supplement the word-wide datapath of a {CGRA}. {W}e show that a time-multiplexed interconnect is beneficial in these coarse-grained systems, reducing the area-energy product to 0.32x the area-energy product of a fully static interconnect. {W}e also show that for our benchmarks, which include single-bit control logic, providing both word and bit-wide interconnect resources further reduces the area-energy product to 0.94x that of an exclusively word-wide interconnect.</p>