A Type Architecture for Hybrid Micro-Parallel Computers

<p>{R}ecently, platform {FPGA}s that integrate sequential processors with a spatial fabric have become prevalent. {W}hile these hybrid architectures ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics remains challenging. {T}he difficulty arises in part from the lack of an agreed upon computational model and family of programming languages. {I}n addition, moving algorithms into hardware is an arcane art far removed from the experience of most programmers. {T}o address this challenge, we present a new type architecture, an abstract model analogous to the von {N}eumann machine for sequential computers, that can serve as common ground for algorithm designers, language designers, and hardware architects. {W}e show that many parallel architectures, including platform {FPGA}s, are implementations of this type architecture. {U}sing examples from a variety of application domains, we show how algorithms can be analyzed to estimate their performance on implementations of this type architecture. {T}his analysis is done without having to delve into the details of any architecture in particular. {F}inally, we describe some of the common features of languages designed for expressing micro-parallelism, highlighting connections with the type architecture.</p>