Latency constraints often arise in the design of digital synchronous circuits because of cyclic dependencies and feedback paths or because of performance requirements. Ad hoc architectural modifications are typically used to improve the performance of circuits. Architectural retiming is a technique for optimizing the performance of latency-constrained circuits.
Overview
Architectural retiming is based on the concept of a negative register, or an anti register, which counteracts the latency effect of a normal register. Negative registers are realized either as a precomputation, shifting the computation backwards in time, or as a prediction, which is nullified a cycle later in case of mispredictions. The circuit's structure and timing are modified, and thus the name architectural retiming.
Architectural retiming unifies and generalizes ad hoc architectural techniques such as branch prediction and bypassing. Preliminary experiments of manually applying architectural retiming to several circuits resulted in an average clock period reduction of 31%. We are currently developing an automated interactive architectural retiming tool, ART.
Researchers
Soha Hassoun and Prof. Carl Ebeling
Slides
You can get a postscript copy of the Architectural Retiming talk from here. (about 2165KB)
References
Hassoun, S. and Ebeling, C., "Architectural Retiming: An Overview", TAU95, Seattle, WA, November, 1995. Postscript of full document is available.
Hassoun, S. and Ebeling, C., "Architectural Retiming: Pipelining Latency-Constrained Circuits", Design Automation Conference, Las Vegas, 1996. Postscript of full document is available.
Hassoun, S. and Ebeling, C., "Sequential Circuit Optimizations Using Precomputation", International Workshop on Logic Synthesis (IWLS-97), June 1997. Postscript of full document is available.
Hassoun, S. and Ebeling, C., "An Overview of Prediction-Based Architectural Retiming", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Dec, 1997.