Susan Eggers

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Susan Eggers, Microsoft Professor of Computer Science and Engineering, joined the department in 1989.  She received a B.A. in 1965 from Connecticut College, and a Ph.D. in 1989 from the University of California, Berkeley.  Her research interests are in computer architecture and back-end compiler optimization, with an emphasis on experimental performance analysis.  With her colleague Hank Levy and their students, she developed the first commercially viable multithreaded architecture, Simultaneous Multithreading, adopted by Intel (as Hyperthreading), IBM, Sun and others. Her current research revolves around instruction set design, processor implementation, thread support, compiler optimization, instruction placement, and protection mechanisms for distributed dataflow machines, namely, WaveScalar.  In 1989 Professor Eggers was awarded an IBM Faculty Development Award and in 1990 an NSF Presidential Young Investigator Award.  She is a Fellow of the ACM and IEEE, a Fellow of the AAAS, and a member of the National Academy of Engineering. Professor Eggers approaches her free time "with a vengeance".  She is a bona fide food snob, is an avid gardener and landscaper, and enjoys active exercise (swimming, golf and physical therapy).

Current Research:

WaveScalar and the WaveCache
The WaveScalar instruction set and its WaveCache implementation were developed in  response to the scaling problems facing tomorrow's superscalar and VLIW processors.  Specifically, they target (1) the increasing disparity between computation and communication costs, (2) the increasing complexity of centralized designs, and (3) the decreasing reliability of shrinking circuit technology.  WaveScalar side-steps these issues with a distributed computing substrate that is composed of thousands of simple, largely identical (and therefore interchangeable) processing elements (PEs).  To reduce communication costs within this substrate, PE's are organized into clusters, each associated with its own store buffer and data cache;  instructions are placed in clusters to minimize both inter-PE and PE-memory communication.

WaveScalar is a dataflow ISA and the WaveCache PEs execute instructions using a dataflow execution model.  Like traditional dataflow architectues, WaveScalar includes instructions for steering values to their consumimg instructions and uses tags to identify different dynamic instances of data.  But unlike previous dataflow architectures, WaveScalar tags identify individual threads and its tag control mechanism is software controlled and distributed throughout the WaveCache. Previous dataflow architectures also required programs to be written in special lanuages that eliminate side effects.  WaveScalar surmounts this shortcoming with wave-ordered memory, a memory-ordering scheme that uses compiler-supplied annotations to preserve total load-store ordering and enables programs written in imperative languages to execute efficiently in the WaveCache.

 WaveScalar's home page

Previous Research:

• Simultaneous multithreading
  
• Dynamic compilation
  
• Coarse-grain, multithreaded architectures
  
• False sharing optimizations
  
• Prefetching on shared memory multiprocessors
  
• Code scheduling
  
• Cache coherency
  
• Other research
  

Last modified onFriday, 21-Nov-2003 22:38:14 PST

 

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