SPR: an architecture-adaptive CGRA mapping tool

<p>{I}n this paper we present {SPR}, a new architecture-adaptive mapping tool for use with {C}oarse-{G}rained {R}econfigurable {A}rchitectures ({CGRA}s). {I}t combines a {VLIW} style scheduler and {FPGA} style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to {CGRA}s. {W}e introduce a latency padding technique that provides feedback from the placer to the scheduler to meet the constraints of a fixed frequency device with configurable interconnect. {U}sing a new dynamic clustering method during placement, we achieved a 1.3x improvement in throughput of mapped designs. {F}inally, we introduce an enhancement to the {P}ath{F}inder algorithm for targeting architectures with a mix of dynamically multiplexed and statically configurable interconnects. {T}he enhanced algorithm is able to successfully share statically configured interconnect in a time-multiplexed way, achieving an average channel width reduction of .5x compared to non-shared static interconnect.</p>