The Triptych FPGA architecture

<p>{F}ield-programmable gate arrays ({FPGA}'s) are an important implementation medium for digital logic. {U}nfortunately, they currently suffer from poor silicon area utilization due to routing constraints. {I}n this paper we present {T}riptych, an {FPGA} architecture designed to achieve improved logic density with competitive performance. {T}his is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. {W}e show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial {FPGA}'s, with comparable performance. {W}e also describe {M}ontage, the first {FPGA} architecture to fully support asynchronous and synchronous interface circuits.</p>