CSE 471: Computer Design and
Organization
Autumn 2000
Last modified on
-
Instructor
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Susan Eggers (eggers@cs.washington.edu)
-
Office: 315 Sieg, 543-2118
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Office Hours: Tue 1:30-2:20 and Fri 10:30-11:20
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TAs
-
Deepak Verma
(deepak@cs)
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Office: 225 Seig, 543-3368
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Office Hours: Mon 10:30-11:30 and Thu 4:30-5:30 (226a)
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Danny Tran (dannyt@U)
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Office Hours: TBA
Assignments
Homework 1: Basic Simulation ( PDF
PS ).
Homework 2: Dynamic Branch Prediction ( PDF
PS )
Homework 3: Out-of-Order Execution with Tomasulo's Algorithm
( PDF
PS )
Files to run Ass1 at Home
Homework 4: Processor Performance Tradeoffs
( PDF
PS )
Homework 5: Organizing Cache Memory Hierarchy
( PDF )
Handouts
Class Overview ( PDF
PS )
Project Report Overview ( PDF
PS)
Sample Project Report 1 ( PDF
PS )
Sample Project Report 2 ( PDF
PS )
SimpleScalar Handout ( PDF
PS )
SimpleScalar ToolSet Documentation ( PDF
PS )
MicroArchitecture for Superscalar Processors (
PDF
PS )
Check outside Susan's door for other handouts taken from journals and
publications.
Lectures
Branch Prediction 1 (PDF
PS)
Branch Prediction 2 ( PDF
PS)
Branch Prediction 3 ( PDF
PS)
Exceptions ( PDF
PS)
Multiple Intruction Issue - Superscalars
( PDF
PS)
Today's in-order pipelines ( PDF
PS)
Dependences & hazards ( PDF
PS)
Tomasulo's algorithm ( PDF
PS)
Physical register pool & register renaming (R10000)
( PDF
PS)
Reorder buffer
( PDF
PS)
VLIW architectures
( PDF
PS)
Midterm topics
( PDF
PS)
Basics of Caches
( PDF
PS)
Advanced Cache Techniques
( PDF
PS)
Memory
( PDF )
MultiProcessors - Mike's Slides.
( PDF )
MultiProcessors - Steve Gibbles slides
( PDF )
MultiProcessors (Snooping) -Luke's slides
( PDF )
MultiProcessors (Directories) -Luke's slides
( PDF )
MultiProcessors (Synchronization) -Luke's slides
( PDF )
Network Processors -Patrick's slides
( PDF )
Simultaneous MultiThreading - Hank's slides
( PDF )
Simultaneous MultiThreading - Steve Swanson's Slides
Wed1 ( PDF )
Wed2 ( PDF )
Fri ( PDF )
Mike's Review slides
( PDF )
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WWW Links
Simple Scalar
Simulator